期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2013
卷号：50
期号：2
出版社：Journal of Theoretical and Applied
摘要：In modern embedded systems, most of them mount with a certain amount of peripherals devices, often a large number of I / O time is consumed in the process of processor access these devices, thereby reducing the overall performance of embedded systems. However, to open up a space in the memory for caching of these device�s data can resolve this problem. UM_BUS (Dynamically Reconfigurable High-speed Serial Bus) with 32 bits wide is the research object of this paper, whose bandwidth can reach 269.5M/s in the ideal condition, but the large number of I/O operations has a serious impact on bus bandwidth utilization. In order to resolve this problem, a data cache mechanism based on the structure and basic theory of cache is designed and implemented for UM_BUS in this paper. After the experimental test, the mechanism is proved to run in the UM_BUS controller driver effectively and improves the bandwidth utilization of UM_BUS significantly, therefore, enhances the performance of the bus to some extent.
