期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2013
卷号：51
期号：3
出版社：Journal of Theoretical and Applied
摘要：A low-power 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) is described in this paper. The downscaling along the pipeline chain decreases the power and area consumption without sacrificing the performance of this converter, and a low power on-chip reference circuit is also helping to reduce power consumption. To improve sampling accuracy of the sub-ADC and minimize the offset of comparator, Digital Error Logic (DEL) is used. The ADC is implemented in a standard 0.13-μm CMOS technology and occupies an active die area of 0.6 mm2. The differential and integral nonlinearity of the ADC are less than 0.27 LSB and 0.63 LSB, respectively. The ADC achieves 8.84 effective number of bits at full sampling rate with a 1-MHz input and consumes 50-mW from a 2.5-V supply.
