期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2013
卷号：54
期号：3
出版社：Journal of Theoretical and Applied
摘要：This study presents a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This model introduces a simple tractable delay formula by incorporating conductance (G) into RC network by preserving the characteristics of the Elmore delay model. The accuracy of the interconnect delay estimates can be improved by deploying the conductance effect. This study proves that the proposed model attains quick steady state condition by incorporating the conductance in a RC network thereby reducing the delay in interconnects. The analysis is validated through extensive simulations on a 250 nm CMOS technology. The SPICE simulation shows the overall figure of merit has an improvement of at least 28% when compared to RC Elmore Model and existing RLC interconnect scheme.
关键词：Elmore Delay; RCG Interconnect; RLC Network; Figure Of Merit; Damping Ratio
