期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2013
卷号：55
期号：1
出版社：Journal of Theoretical and Applied
摘要：A lower power current comparison based domino logic 4*4 Wallace tree multiplier is proposed. Here the multiplier is designed by using low leakage high speed full adders. These full adders uses current comparison based domino logic to achieve low leakage and high speed. The technique which is utilized in this paper is based on comparison of mirrored current of the pull-up network with its worst leakage case current. This technique decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates to implement fast and robust circuits. So that the leakage current and power consumption and delay are reduced. The proposed 4*4 Wallace tree multiplier using current comparison based domino logic full adders was simulated using Mentor graphics ELDO in the temperature of 27o C, which is operated in 3 GHz shows half of the power reduction when compared to the 4*4 Wallace tree multiplier using standard full adders.
关键词：Domino Logic; Wallace Multiplier; Power Dissipation; Full Adder; CMOS Logic
