期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：60
期号：1
出版社：Journal of Theoretical and Applied
摘要：This RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces two RC4 key stream bytes per clock cycle. We have optimized and implemented our proposed design using Verilog description, synthesized with 45nm technology. The proposed design has a total area of 138459um2 and shows a power consumption of 382.0935mW.The proposed circuit has a higher operating frequency of 1.387GHz compared to 1.22GHz which is 8.37% higher than the conventional RC4 circuit. The throughput of the proposed RC4 circuit is found to be 22.192Gbps.
