期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：63
期号：2
出版社：Journal of Theoretical and Applied
摘要：In VLSI circuits, peak power and RMS current reduction are the challenging tasks. Both power density and peak power are proportional to each other. If these parameters are reduced, it may lead to a timing violation and logic failures. In order to overcome these failures, Clock Control Strategy based Clustering Method (CCSCM) is proposed. In the proposed clustering method, we design to reduce the path delays, to find the inequality paths and to make it equality through a slack values using slack variables. In previous method, benchmark circuits are used which results in finding difficult in a slack delay and RMS current reduction. But in our proposed algorithm, CMOS full adder is developed which make use of finite impulse response (FIR) filter design based on the 180 NM technology. A 180 nm generation logic technology has been developed with high performance 140 nm LGATE transistors, six layers of aluminum interconnects and low-e SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power. The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiO2 inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 mm2 6-T cell size have been built on this technology as a yield and reliability test vehicle.
关键词：LGATE; Clock Control Strategy Based Clustering Method; FIR Filter; CMOS Full Adder; Path Delay; Slack Value; RMS Current Reduction.
