期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：63
期号：2
出版社：Journal of Theoretical and Applied
摘要：In this paper, we present a partially parallel Quasi cyclic Low Density Parity Check decoder architecture for WiMAX IEEE 802.16e standard. Two phase message passing Min-sum decoding algorithm is used to decode the Low Density Parity Check codes. The decoder is designed for code rate � and code length of 576 bits and 2304bits. The decoder is easily configurable to support different code lengths of WiMAX IEEE 802.16e standard. In the proposed architecture, two phases of decoding are overlapped to increase the throughput and hardware utilization is increased. In this work , a novel configurable variable node processor is introduced to increase the hardware utilization. The proposed architectures are implemented on Xilinx Virtex V xc5vlx110-3-ff676 FPGA.
关键词：Field programmable Gate Arrays; Min-sum Decoding Algorithm; Quasi cyclic Low Density Parity check Codes.
