首页    期刊浏览 2024年11月25日 星期一
登录注册

文章基本信息

  • 标题:FPGA IMPLEMENTATION OF COEFFICIENT DECIMATED POLYPHASE FILTER BANK STRUCTURE FOR MULTISTANDARD COMMUNICATION RECEIVER
  • 本地全文:下载
  • 作者:P. KALPANA DEVI ; R. S. BHUVANESHWARAN
  • 期刊名称:Journal of Theoretical and Applied Information Technology
  • 印刷版ISSN:1992-8645
  • 电子版ISSN:1817-3195
  • 出版年度:2014
  • 卷号:64
  • 期号:2
  • 出版社:Journal of Theoretical and Applied
  • 摘要:Coefficient decimated polyphase FIR filter bank structure implemented for receiving narrow band channels effectively in multistandard environment. Reonfigurability in multirate filtering is required to design a prototype filter bank structure for selecting the distinct polyphase sub filters and taps for different standards. Coefficient decimation (CD) based filter bank can offer a good trade-off between reconfigurability and low complexity which satisfy most of the requirements for SDR receivers. This paper proposed a method of filter bank technique which reduces the overall complexity of the design. The pro-posed filter structure has been synthesized on 0.18�m CMOS technology single core Field programmable gate array. Synthesis report proved the reduced device utilization for the proposed structure.
  • 关键词:FIR Filters; Reconfigurabality; Coefficient Decimation; Polyphase Filter; Multistandard; Channelization
国家哲学社会科学文献中心版权所有