期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：64
期号：2
出版社：Journal of Theoretical and Applied
摘要：The reconfigurable processor design which utilizes platform such as Field Programmable Gate Array (FPGA) has offered several advantages in minimizing the non-recurring engineering cost and to reduce the time-to-market for processor-based products. However, when any modification is made to the processor architecture, the same information needs to be relayed to the assembler in order to generate the correct object files. This paper presents the assembler design techniques for a reconfigurable reduced instruction set computer (RISC) processor called UTeMRISC03. The processor is a soft-core processor, which is described in Verilog and its instruction set architecture (ISA) has been expanded to include a custom instruction. Thus, the assembler would have to adjust according to the changes being made to the ISA. One-pass and two-pass techniques have been adopted during the construction of the assembler and the generated object files are used as the initialization files during the FPGA implementation of the processor core. The assembler has been successfully developed by using both techniques and the object files are verified by executing the processor core in the Xilinx Spartan-3A FPGA chip. For comparisons, the assembling execution times for both techniques have been recorded and the one-pass technique has been able to complete the assembling process in half of the time it took for two-pass technique. The design techniques adopted in this paper will serve as the base platform with the aim of establishing a full-customizable assembler for reconfigurable soft-core processor in the near future.
