期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：64
期号：3
出版社：Journal of Theoretical and Applied
摘要：Carry select adder is the one among the fastest adder used in the data processing element however conventional carry select adder(CSLA) are still area-consuming due to multiple pair of Ripple carry adder structure. This proposed work is solely dedicated to develop a low power and area efficient half adder based carry select adder architecture (CSLA) using common Boolean logic (CBL). It only needs one Half-adder to perform summation operation for carry zero and common Boolean logic (CBL) for carry one respectively. Half adder has been designed using one XOR gate and one AND gate. CBL needs only one OR gate and one NOT gate. Through the multiplexer, we can select the correct output in the final stage according to the logic state of the carry-in- signal. Based on this modification 8-bit, 16-bit, 32-bit, 64-bit square root carry select adder (SQRT CSLA) architecture has been developed and compared with the regular SQRT CSLA structure and modified SQRT CSLA has been developed using binary to excess-1 converter (BEC). This proposed design on an average reduces area by 53.77%, power consumption by 93% and power-delay product (PDP) by 75.71%, but with some amount of increase in the delay as compared with regular SQRT CSLA architecture. The result analysis shows that the proposed CSLA architecture achieves better performance in term of area, power and power-delay product than the regular and modified SQRT CSLA structure.
