期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：65
期号：2
出版社：Journal of Theoretical and Applied
摘要：This paper addresses on two different architectures of digital decimation filter design of a multi-standard Radio Frequency (RF) transceivers. Instead of using single stage decimation filter network, the filters are implemented in multiple stages using FPGA to optimize the area and power. The proposed two types of decimation filter architectures reflect the considerable reduction in area & power consumption without degradation of performance. The filter coefficients are derived from MATLAB and the filter architectures are implemented and tested using Xilinx SPARTAN FPGA .The Xilinx ISE 9.2i tool is used for logic synthesis and the Xpower analysis tool is used for estimating the power consumption. First, the types of decimation filter architectures are tested and implemented using conventional binary number system. Then the two different encoding schemes namely i.e. Canonic Signed Digit (CSD) and Minimum Signed Digit (MSD) are used for filter coefficients and then the architecture performances are tested .The results of CSD and MSD based architectures show a considerable reduction in the area & power against the conventional number system based filter design implementation.
关键词：Digital Transceiver; Multi-rate Digital Filter; Multistage Decimation Filter; FPGA; Area Reduction; Low Power Design.
