期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：66
期号：1
出版社：Journal of Theoretical and Applied
摘要：High performance, energy efficient logic style is a popular research topic in the field of very large scale integrated (VLSI) circuits. A complex constant logic style is used to implement a logic expression to achieve high speed operation. This logic style is well suited for arithmetic circuit where critical path comprises of large cascaded inverting gates. Multiplication is a most utilized arithmetic operator that forms a part of filters, convolvers, and transforms processors in digital signal processing applications. This paper focuses on the design of the Wallace tree multiplier, Baugh wooley and Array multiplier using static logic style, dynamic logic style and compound constant delay logic style .The performance of energy delay product of Wallace tree multiplier, array multiplier and Baugh wooley multiplier using compound constant delay logic style is reduced considerably while compared to static and dynamic logic style.
关键词：Wallace Tree multiplier; Array multiplier; Carry Skip adder; Cadence and Baugh Wooley Multiplier
