期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：66
期号：1
出版社：Journal of Theoretical and Applied
摘要：This paper is focused on the practical and designing aspects of a cascaded multilevel inverter using synchronous sequential circuits. The performance of the inverter has been improved by using a digital logic algorithm for required pulse width modulation. The digital logic algorithm has been exposed to give the superior performance in load voltage and total harmonic distortion. The synchronous sequential circuit based multilevel inverter offer several advantages like simple structure, easy to identify the fault, cost-effective, improved functional performance and low power consumption. The output voltage performance of proposed strategy has been confirmed through simulation and hardware investigations.
关键词：Digital Logic Control (DLC); Synchronous Sequential Circuits (SSC); Total Harmonic Distortion (THD); Cascaded Multilevel Inverter (CMLI); Pulse width modulation (PWM).
