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  • 标题:NETWORK INTRUSION DETECTION SYSTEM: AN IMPROVED ARCHITECTURE TO REDUCE FALSE POSITIVE RATE
  • 本地全文:下载
  • 作者:P.BRINDHA ; Dr.A.SENTHILKUMAR
  • 期刊名称:Journal of Theoretical and Applied Information Technology
  • 印刷版ISSN:1992-8645
  • 电子版ISSN:1817-3195
  • 出版年度:2014
  • 卷号:66
  • 期号:2
  • 出版社:Journal of Theoretical and Applied
  • 摘要:Counting Bloom Filter (CBFs) is widely employed in networking applications. They support membership queries with minimal error and surmount the drawback of Bloom filters. However, they engross large amount of memory. A new Sidon sequence based CBF is introduced to improve the competency of the CBFs. Unlike CBF, the hashed Variable increment is queried for its present. This method achieves 24% of the improvement in false positive rate and a lower inundate probability bound than CBF. The proposed work is described in Verilog and simulated using Xilinx 12.1. The functional block is implemented as hardware using Virtex 4 (XC4VSX25) Field Programmable Gate Array (FPGA). It is observed that the hardware complexity and memory overhead increases, which could be a trade-off for improving FPR in order to increase the Network Security.
  • 关键词:Intrusion Detection; Bloom Filter; Sidon sequence; Counting Bloom filter; False Positive Rate.
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