期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：66
期号：3
出版社：Journal of Theoretical and Applied
摘要：Arithmetic and Logic Unit (ALU) is one of the frequent and the most fundamental component in low power processor design. Besides Power consumption due to clock gated ALU can be significant in high performance systems. In general the functionality of ALU is a mixture of arithmetic and logic operations which are realized by means of combinational circuits. In this research work the power flow analysis of clock gated ALU circuits is analyzed and optimization of clock gated ALU power supply unit is done through special handing technique. The proposed design which controls the power supply unit of ALU via Clock Gated Double Edge Triggered (CGDET)flip-flop technique which outperforms the traditional Clock Gated Single-Edge-Triggered (CGSET) flip-flop and it reduces the power consumption by 2.2% while keeping the same data rate. In contrast with existing techniques the proposed method has simpler structure, lower delay time, condensed Power Delay Product (PDP), Energy Delay Product (EDP) and Static current has been tabulated. The work suggests that clock gated double edge triggering provides optimized power management for ALU design.
关键词：Clock Gated Single-Edge-Triggered (CGSET) Flip-Flop; Clock Gated Double- Edge -Triggered (CGDET) Flip-Flop; Power Delay Product; Energy Delay Product; Arithmetic And Logic Unit
