期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：67
期号：1
出版社：Journal of Theoretical and Applied
摘要：The ultra-low power requirements of emerging implantable and wearable biomedical devices, necessitates, novel power management schemes. In this paper, we focus our attention on large DSP data path operators such as multipliers and MAC circuits, where lowering the energy per operation is of greater importance. These form the heart of a majority of commercial DSP Processor data path units. We examine architectural choices for merged MAC circuits and formulate a high-speed/low-power MAC architecture.An efficient hardware architecture for Multiply Accumulate (MAC) unit based on a modified Dadda tree multiplier is proposed and validated in full custom environment in standard cell 180nm technology. The partial products reduction block is completely designed using the novel binary compressors and the addition module is implemented using a new less complex modified full adder based on XNOR. Feeding the bits of the accumulated operand into the summation tree before the final adder helps to increase the speed .The final adder is implemented using ripple carry adder. The resulting MAC is implemented and compared with the existing low power designs. The simulation results show that the proposed implementation is faster and consume less power than similar implementations making it a viable option for efficient designs. The 32x32 bit MAC unit designed using proposed full adder as the basic building block gave a power saving of 24.27% over 32 bit MAC designed using SERF full adder and 35.07% power savings over 32 bit MAC designed using conventional 28T full adder.
关键词：Wallace; Compressor; Low power; MAC; SERF full adder
