期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：67
期号：2
出版社：Journal of Theoretical and Applied
摘要：New technologies are emerging to take the challenges in the wireless communication. According to the requirements for the next generation technologies have led to unparalleled insist for high speed architectures for complex signal processing applications. In this paper, we propose a modified DMWT architecture based on CardBal filter. The DMWT coefficients that are fractions are converted to integers and are modified to reduce the number of multiplications and additions. The reduced CardBal filter coefficients are used to process the data, thus reducing the computation complexity and making it suitable for FPGA implementation. The design operates at maximum frequency of 300MHz and consumes less than 1% resources and thus is suitable for real time applications optimizing area, speed and power. The model is tested for its functionality using HDL code and is synthesized using Xilinx ISE targeting FPGA.
