期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：67
期号：3
出版社：Journal of Theoretical and Applied
摘要：In many digital computers multipliers plays vital role to improve the performance of the system. The speed of the processor greatly depends on high speed multipliers. On the other hand pipeline technology plays an important role in present parallel computers in improving the speed of the computer. In the present paper high speedVedic multiplier is designed and analysed by inserting a pipeline in the process of computation.The computation speed is considerably improved with pipeline when compared with conventional Vedic multiplier. The proposed pipelined Vedic multiplier was implemented in TSMC 65nm CMOS Technology consumes 57mWatts power when operated at 100MHz.
关键词：Pipeline; Vedic Multiplier; Throughput; High Speed
