期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：68
期号：1
出版社：Journal of Theoretical and Applied
摘要：In this paper, a Novel Hybrid ADC consisting of two-step quantizer which has Flash ADC and SAR ADC along with Resistor String DAC is designed and implemented. This Hybrid ADC improves the speed by employing Flash ADC and resolution and power reduction can be achieved by utilizing SAR ADC. The Hybrid architecture carrying 12 bits as resolution, input frequency as 100MHz and sampling frequency is 1GHz. CMOS level schematic diagram of sub-blocks has been designed and implemented using Cadence Virtuoso 180nm technology at an operating voltage of 1.8 V. Layout design is captured using Virtuoso and then it is optimized for area. Based on the obtained result, INL and DNL has been identified as +0.034V to � 0.001V and + 0.06V to -0.05V respectively. The performance results show that the architecture achieves low power, high speed and less area.
关键词：Sample and Hold Circuit; Comparator; Transmission Gate; Hybrid ADC; Two-step Quantizer; SAR and Flash ADC.
