期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：69
期号：3
出版社：Journal of Theoretical and Applied
摘要：The conventional high level synthesis techniques target DSP algorithms onto architectures using basic functional units such as adders or multipliers. In this paper, a scheme for the partitioning of the data flow graph of a DSP application for a high-level synthesis aimed at a design using multi-modules is proposed. In the propose scheme, the regularity characteristics of DSP application are exploited. Moreover, in order to reduce the number of distinct modules, the near-isomorphism sub-graphs represents the modules are merged together by multiplexing them in time to produce a single adaptable module. This merging process enables the reuse of the adaptable modules by partially reconfiguring them at run time to realize different modules during the running of the DSP data flow graph. Furthermore, a novel reconfigurable multiplier multiplier is incorporated in the proposed synthesis technique. It is seen that a small overhead in terms of the architecture�s controller is needed by the modules in order for them to be adapted to perform different computations (multi-modes).
关键词：Architectural Synthesis; Reconfigurable Multimodule; Time Scheduling; Reconfigurable Processing Units
