期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2014
卷号：70
期号：3
出版社：Journal of Theoretical and Applied
摘要：Many multimedia and digital signal processing systems are desirable to maintain a fixed format and to allow little accuracy loss to output data. The objective of this paper is to design a fixed width modified booth multiplier with high error performance. And the need to derive an effective error compensation function that makes the error distribution more symmetric and centralized in the error equalized to zero. The compensation circuit is mainly composed of simplified sorting network and this can achieve a tiny mean and mean square error as compared to the other circuits. The odd even sorting networks used for error compensation are composed of appropriately connected comparators. The simplified form of sorting network consist of neither NAND, NOR, AND-OR INVERTER (AOI) and OR-AND-INVERTER (OAI). In fixed width modified Booth multiplication, to reduce the number of partial products by a factor of two, modified booth encoding is used. The software used for the simulation of this circuit is Altera-Quartus II. The RTL code is generated using the above software. The implementation of the circuit is done using DE1 board.
关键词：Booth Multiplier; mean square error; partial products
