期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2015
卷号：73
期号：3
出版社：Journal of Theoretical and Applied
摘要：Fully associative caches expend maximum energy among caches for any size. The blocks of fully associative cache are searched in parallel during address mapping. This paper proposes architecture to reduce the power consumption in fully associative cache. The cache blocks are assumed to operate in one of two modes - on or off. The model consists of introducing one bit per block which is enabled on block occupancy. This bit is checked before the address match is performed. This saves power consumption in address comparison. The proposed model is simulated with SPEC2K benchmark. An improvement in power consumption of 59% with no change in average memory access time is observed for the chosen parameters.
