期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2015
卷号：74
期号：3
出版社：Journal of Theoretical and Applied
摘要：High performance phase frequency detector (PFD) is one of the key modules in high speed delay-locked loop (DLL). The operation of DLL depends on the performance of its detector. The demand for the reduction of power dissipation in CMOS design is a challenge in order to optimize circuit power consumption. A low power dynamic pseudo-PMOS PFD is proposed to make DLL system more reliable. In this work NOR gate of typical TSPC PFD is replaced with a low power dissipation pseudo-PMOS AND gate built of 3 PMOS transistors. Pseudo-PMOS AND integrated into proposed TSPC PFD to run maximum frequency at 1G Hz with 1.8 V input power supply. This proposed PFD has been implemented in Mentor Graphics 0.18 μm CMOS process technology and consumed 163.36 �m2 active layout area with 206 nW total power dissipation will further trim down the total cost of the DLL.
关键词：DLL; Dynamic PFD; Low Power PFD; Low Noise PFD; Pseudo-PMOS
