期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2015
卷号：79
期号：2
出版社：Journal of Theoretical and Applied
摘要：In low-power digital design, especially in shift registers, flip-flops (FF) plays a significant role. In shift registers, the power consumption of system clock is estimated to be half of the overall system power. Therefore, selecting the right FF is very important for designing an compact size and low power shift register. In this paper, a review of different FF designs that have been applied for different shift register (SIPO, PIPO, SISO and PISO) is presented. The connection between FFs parameters and shift registers is also discussed. FFs architecture is evaluated via its average power, delay and power delay product. Comparative study showed that FFs have great effect on the performance quality of shift registers.
