期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2015
卷号：81
期号：3
出版社：Journal of Theoretical and Applied
摘要：In this paper, a modified programmable twisted ring counter (MPTRC) based on-chip test generation scheme is proposed. It is used as built-in-self-test (BIST) pattern generator for high performance circuits with simple test control. This method is used to achieve low power and reduced test time for digital circuits. The MPTRC module is designed with Cadence NClaunch platform using Verilog HDL and synthesis done by using Cadence RTL compiler with 0.18�m technology. The simulation results show about 13.46% power reduction compared with conventional programmable twisted ring counter (PTRC) based design.
关键词：Built-in-self-test (BIST); System-on-chip (SoC); Ring counter; Twisted-ring-counter (TRC); Programmable twisted ring counter (PTRC).
