出版社：University of Malaya * Faculty of Computer Science and Information Technology
摘要：This paper presents an electronic design automation (EDA) software for generating synthesizable VHDL modules for hardware applications of multimedia data processing. The tool provides a rapidprototyping design environment by enabling dynamic storage and retrieval of reusable modules, parameterized design entry, hierarchical design exploration, listbased component interface insertion, and block diagram view of designs. This produces a design environment, which enables fast design development cycle by improving design productivity to meet the fast evolving standards of multimedia formats. A test case design of a JPEG decoder has been built using the tool. Implementation of the design in FPGA has proven the capability of the tool in handling large and complex designs.
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