期刊名称：International Journal on Smart Sensing and Intelligent Systems
印刷版ISSN：1178-5608
出版年度：2017
卷号：10
期号：2
页码：327-340
出版社：Massey University
摘要：In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality of the adders have been verified using Verilog hardware description language and synthesized in Xilinx ISE. The device chosen for implementation is Virtex 6 (XC6VLX240T) with FF1156 package. Simulation results show that Wallace tree adder is the fastest adder and consumes least amount of power. The Wallace tree adder also consumes the least amount of hardware resources as per the synthesis results.
关键词：Multi-operand adders; synthesis results; tree adders; Verilog
