期刊名称：Journal of Theoretical and Applied Information Technology
印刷版ISSN：1992-8645
电子版ISSN：1817-3195
出版年度：2017
卷号：95
期号：10
出版社：Journal of Theoretical and Applied
摘要：Cryptography establishes a secure channel for data communication between sender and receiver. Nowadays, millions of online transactions happen in seconds throughout the world like trading, banking, e-commerce, and social networking etc., exchanges data among users. Evolution in internet led to increase in number of hackers, cyber attacks over network, network security has become a major issue in present era data protection has become significant, such that an unbreakable encryption technology should be designed in order to provide security for the data. The advent of VLSI technology has grown enormously in the last two decades by extending its prominence towards network security where mainly information processing cryptography has gained popularity in this field. This paper presents a module in cryptosystem is partially reconfigurable (PR) in run time which serves two purposes. One module for dynamic key generation mechanisms and second module for inverse permutation block in Data Encryption Standard (DES) and shift rows block in Advanced Encryption Standard (AES) cryptography techniques which play a vital role in data security. A new approach with Deoxyribonucleic Acid(DNA)structure have four nucleotides which are named as A (Adenine), C (Cytosine), G (Guanine) and T (Thymine) are the elements existing in DNA mechanism is applied on both cipher and key are merged and transmitted along a channel in protein form which enhances the security. Run time evolvable hardware like, Field Programmable Gate Array (FPGA) architecture and its behavior changes dynamically with partial reconfiguration are suitable for wide variety of applications which can configure to implement custom designs and needs. Encryption Techniques are designed using Verilog HDL, synthesized in Xilinx simulated with ISIM simulator and implemented on Virtex FPGA architecture. Dynamic keys and reconfigurable modules are generated by loading Partial bit streams from CF Card are configured to FPGA by issuing commands in serial Terminal through MicroBlaze Processor.
