首页    期刊浏览 2025年12月05日 星期五
登录注册

文章基本信息

  • 标题:Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units
  • 其他标题:Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units
  • 作者:Vašíček, Zdeněk ; Sekanina, Lukáš
  • 期刊名称:COMPUTING AND INFORMATICS
  • 印刷版ISSN:1335-9150
  • 出版年度:2010
  • 卷号:29
  • 期号:6+
  • 页码:1359-1371
  • 语种:English
  • 出版社:COMPUTING AND INFORMATICS
  • 摘要:A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.
  • 关键词:Cartesian genetic programming; hardware accelerator; evolutionary circuit design; FPGA
Loading...
联系我们|关于我们|网站声明
国家哲学社会科学文献中心版权所有