期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2016
卷号：7
期号：1
页码：1
DOI：10.5121/vlsic.2016.7101
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：The use of asynchronous design approaches to construct digital signal processing (DSP) systems is arapidly growing research area driven by a wide range of emerging energy constrained applications suchas wireless sensor network, portable medical devices and brain implants. The asynchronous designtechniques allow the construction of systems which are samples driven, which means they only dissipatedynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronousdesign over conventional synchronous circuits allows them to be energy efficient. However theimplementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandardsynchronous design tools and modelling languages. This paper devises a novel asynchronousdesign for a finite impulse response (FIR) filter, an essential building block of DSP systems, which issynthesizable and suitable for implementation using conventional synchronous systems design flow andtools. The proposed design is based on a modified version of the micropipline architecture and it isconstructed using four phase bundled data protocol. A hardware prototype of the proposed filter has beendeveloped on an FPGA, and systematically verified. The results prove correct functionality of the noveldesign and a superior performance compared to a synchronous FIR implementation. The findings of thiswork will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy andperformance benefits.
