期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2016
卷号：7
期号：2
页码：1
DOI：10.5121/vlsic.2016.7201
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style isrobust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is oftenfound in critical paths of various large scale high performance circuits. Yet, due to high switching activitythey are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, wepropose a method of designing circuit using mixed CMOS logic style, taking advantages of both static andDomino logic styles. For a given circuit, we extract the unate and binate components using a unatedecomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power,area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binateblocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of ourapproach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and22% in transistor count with 12% more power dissipation compared to circuits with only static CMOSlogic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications.
