期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2016
卷号：7
期号：3
页码：13
DOI：10.5121/vlsic.2016.7302
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Power consumption reduction is transpiring drift in area of VLSI digital signal processing. This gives riseto need of minimization of silicon area which is done by folding algorithm. As silicon area decreases powerconsumption of a circuit decreases. Folding is an algorithm which reduces silicon chip area by combiningvarious arithmetic operations into one operation by time scheduling technique. It is applied on iterativedata flow graph with appropriate folding set. Least mean square algorithm alters coefficients of Adaptivefilter in order to achieve desired output. Proposed work is focused on design of efficient VLSI architecturefor LMS adaptive filter aims at reducing mainly area which results in power consumption reduction andhardware complexity. LMS filter structure used here is called non-canonical as transpose FIR structure isused. Results show that numbers of adders are reduced by 37.5 % and multipliers by 33.33% withoutchanging characteristics of filter.
关键词：VLSI signal processing; folding; cutset retiming; iterative DFG; non-canonical.
