期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2016
卷号：7
期号：4
页码：47
DOI：10.5121/vlsic.2016.7405
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Hazard in digital circuits is unnecessary transitions due to gate propagation delay in that circuit. Hazardsoccur due to uneven delay offered in the path of the various ongoing signals. One of the important reasonsfor power dissipation in CMOS circuits is the switching activity .This include activities such as spuriouspulses, called glitches. Power optimization techniques that concentrate on the reduction of switchingpower dissipation of a given circuit are called glitch reduction techniques. In this paper, we analysevarious Glitch reduction techniques such as Hazard filtering Technique, Balanced Path Technique,Multiple Threshold Technique and Gate Freezing Technique. We also measure the parameters such asnoise and delay of the circuits on application of various techniques to check the reliability of differentcircuits in various situations.
关键词：Glitch; Power dissipation; Gate freezing; balanced path delay; multiple threshold transistor; Hazard;filtering; Noise; Delay and switching activity
