期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2017
卷号：17
期号：11
页码：131-135
出版社：International Journal of Computer Science and Network Security
摘要：The Charge Pump Phase Locked Loop (CP-PLL) are widelys used component in modern day highly integrated electronic systems involved in wireless communication and smart system applications to perform several functions like frequency synhesis, clock recovery, and clock generation. The CP-PLL is switching device becuase of the triggering nature of the digital phase detector. Mostly a second order CP-PLL is utilized in comsumer electronics applications. The voltage controlled oscillator (VCO) generates signal with frequency excursion due to a non-linear effect, called jump frequencies arising due to the filter impedance. These jump frequencies may lead to overload the VCO. This paper highlights the overload situation of the two different architecture of mixed-signal PLLs. The simulations are performed using fast and efficient Event Driven (ED) model. The effect of jump frequencies on both architectures of the CP-PLL is analyzed.
关键词：Phase locked loop; VCO; Overload; non-linear system; frequency jumps.
