期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2017
卷号：8
期号：6
页码：15
DOI：10.5121/vlsic.2017.8602
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financialapplications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm.Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its naturalproperties. The AES architecture with the enhanced mix column to be proposed with reduced number oftransistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AESArchitecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOStechnology 0.25 μm. By using the net list generations, the proposed AES Architecture is analyzed regardingthe VLSI design environment. The simulation results of the proposed structure are performed with theminimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOStechnology based AES Algorithm is integrated into the backend based chip technology.
