摘要：Subheading: Benchmarking of Radix-2 Sequential Multiplication using five Xilinx FPGA families. Background: This paper presents description on the implementation of fast radix-2 sequential multiplier using repeated carry save addition (CSA) method with variable data path sizes ranging from 8 bits to 1024 bit. Objective: The main objective of this paper is to achieve the best achievable time delay reduction with better performance ( i.e. frequency) running on FPGA platforms and prove their applicability in high performance reconfigurable computing. Methods: The design was implemented using VHDL description language and synthesized using five different Xilinx FPGA chip families, namely: vertix7, kintex7, artix7, zynq7 and spartan6. Rigorous tests were conducted and analyzed in terms of maximum frequency and total delay time of the FPGA design as well as the hardware utilization. Results: The results on the code synthesizing demonstrated that the proposed 1024-bit sequential multiplier with kintex7 chip family outperforms others with a maximum frequency of 296 MHz, while Spartan 6 recorded the lowest frequency with 140 MHz. Conclusion: The performance of the proposed multiplier-based CSA was benchmarked against other state-of-the-art designs which results reflected its superiority in terms of throughput of two or more multiple times as compared to others.
关键词：Adder ; Coprocessors ; Integrated circuit synthesis ; field programmable analog arrays ; Digital arithmetic ; Sequential multiplication; Hardware description language (HDL) .
