期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2011
卷号：8
期号：4
出版社：IJCSI Press
摘要：The work of motion estimation is highly used in the surveillance applications especially for military activities. One of the key elements of many video compression schemes is motion estimation, for the removal of video temporal redundancy. This paper presents an architecture for motion estimation using modified Full Search BM algorithm eliminating the SAD distortion criterion. The quality of the algorithm used was compared with Full Search through software implementations. The quality of BMA results was considered satisfactory, The designed hardware considered a search range of [-25, +24], with blocks of 16x16 pixels. The architecture was described in VHDL and mapped to a Xilinx Virtex-II Pro VP70 FPGA. Defining efficient techniques for video processing is of special interest due to the existence of a wide variety of applications in the fields of entertainment, computer vision, surveillance, security etc. The different techniques are mainly compared in the terms of algorithmic efficiency, hardware requirement, processing speed and error performances. In this paper we have designed a new parallel processing architecture to perform the video analysis for motion estimation. We have also done the simulation and FPGA based synthesis of the proposed architecture for the most commonly used target hardware to analyze the hardware cost.
关键词：Motion Estimation; Macro Blocks; Zero Matrix; Edges; Frame
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