期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2011
卷号：8
期号：6
出版社：IJCSI Press
摘要：As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. Network-on-Chip architectures have a wide variety of parameters that can be adapted to the designers requirements. This paper proposes a performance and power network on chip simulator (PPNOCS) based on SystemC to explore the impact of various architectural level parameters of the on-chip interconnection network elements on its performance and power. PPNOCS supports an arbitrary size of mesh and torus topology, adopts five classic routing algorithms and seven synthetic traffic patterns. Developers also can develop and verify their own network design by modifying the corresponding modules. Experiments of using this simulator are carried out to study the power, latency and throughput of a 4x4 multi-core mesh network topology. Results show that PPNOCS provides a fast and convenient platform for researching and verification of NoC architectures and routing algorithms.
