期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2012
卷号：9
期号：3
出版社：IJCSI Press
摘要：In recent years, as System on Chip design research is actively conducted, a large number of IPs is included in a system based on a Network on Chip(NoC). Different interfaces specification of IP cores and different flow controls are used by router. They raise a considerable difficulty for adopting NoC techniques. To facilitate the use of the NoC techniques an efficient design of the network interface (NI) unit that connects the switched network to the IP cores is required. In this paper, we present a new NI architecture for NoC with low latency and jitter constraints. We introduce a new distributed buffer structure that increases area and reduces latency and jitter. We present how we can apply the decoupling between computing and communication by proposing a modular architecture. The low latency and minimal jitter between packets are obtained through the separation between header and payload memories. This separation enables the NI to receive a new packet before the end of the transmission of a previous packet. The modular design is obtained through the separations between injection and extraction path and between IP and network sides. The latter separation allows IPs and NoC to be designed independently from each other. For evaluating the efficiency of this approach, we use AHB standard at the IP side and we use the most three used flow controls in NoC. A performance study was conducted and NI designs were synthesized with ST 0.13#956;m CMOS technology using four different libraries. Experimental results show that the proposed NIs allow better results in terms of latency, jitter and dissipated power relatively to the current published state-of-the art NI architectures.
关键词：Network Interface; Network on Chip; ASIC; Low latency; Low power
