期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2012
卷号：9
期号：4
出版社：IJCSI Press
摘要：In this paper, a hybrid synchronous and asynchronous digital FIR filter is designed and implemented in FPGA using VHDL. The digital FIR filter of high throughput, low latency operating at above 1.3 GHz was designed. An adaptive high capacity pipelined was introduced in the hybrid synchronous asynchronous design of the filter. The degree of the pipelining is dynamically variable depending upon the input. Concurrent execution of software or program can be achieved in FPGA through parallel processing. The designed digital FIR filter is simulated using ModelSim and implemented using Xilinx. The simulation results are presented for different order such as 3, 6 and 15. The FIR filter designed is synthesized in Xilinx 9.1i and the device utilization report is presented for filter of order 3, 6 and 15.
关键词：FPGA; Asynchronous pipeline; dynamic logic; FIR Filter
