期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2012
卷号：9
期号：5
出版社：IJCSI Press
摘要：Concurrent processors incorporated on a single chip for performing computations can be troublesome because as the size of problems increase, the execution time also increases. In order to make sure that the execution time is reduced, a traditional approach is used that implies that the problem will be computed by an array of processors that are interconnected over a high-speed interconnection network. A Duplicated process is presented in this paper to handle the complexity of computing arithmetic of AUV localization operation. A single clock cycle is sufficient for performing all the operations in this process. This type of process is referred to as Duplicated because each cell incorporates a variety of duplicated multipliers and adders. The minimum number of clock cycles are needed to complete each iteration. However, each cell takes up more area on the chip. The calculation rate of the duplicated process is high despite the fact that its throughput is significantly limited by the small number of cells that can be accommodated by the FPGA.
关键词：Embedded system design; FPGA system design; concurrent processing; underwater detection.
