期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2012
卷号：9
期号：5
出版社：IJCSI Press
摘要：The superscalar pipeline is something that the REP architecture resembles. The features that are similar in both architectures include rename, decode, fetch as well as in-order front-ends parts as substituted by dispatch units. The physical register file, execute unit, dynamic scheduler and task queue are contained by the out of-order execution core. The architecture also contains the REP that beholds an integrated system of shared-memory. A number of experiments with realistic benchmarks and an FPGA environment are used to synthesize design. The experiments conducted yielded in results that prove that the new architecture of the REP leads to higher performance of applications because of decreased processing time. And the core reason for the deduction of processing time is the simplified complexity of the frequency and area of the architecture. The results show that the least error tolerance is 1m by particle filter. Also, the optimum iteration level is 20 to get enhanceable navigation data for AUV.
