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文章基本信息

  • 标题:Several AES Variants under VHDL language In FPGA
  • 本地全文:下载
  • 作者:Sliman Arrag ; Abdellatif Hamdoun ; Abderrahim Tragha
  • 期刊名称:International Journal of Computer Science Issues
  • 印刷版ISSN:1694-0784
  • 电子版ISSN:1694-0814
  • 出版年度:2012
  • 卷号:9
  • 期号:5
  • 出版社:IJCSI Press
  • 摘要:This paper provides four different architectures for encrypting and decrypting 128 bit information via the AES. The encryption algorithm includes the Key Expansion module which generates Key for all iterations on the fly, Double AEStwo-key triple AES, AESX and AES-EXE. These architectures are implemented and studied in Altera Cyclone III and STRATIX Family devices.
  • 关键词:double AES ; Triple AES;AESx;AES;exe; VHDL code.
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