期刊名称：International Journal of Computer Science Issues
印刷版ISSN：1694-0784
电子版ISSN：1694-0814
出版年度：2014
卷号：11
期号：3
出版社：IJCSI Press
摘要：In recent years, reversible logic circuits are increasingly used in power minimization and having applications such as low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. Under ideal conditions, reversible logic gates produce zero power dissipation. The main motivation behind the study of this technology is aimed at implementing reversible computing where they offer what is predicted to be the only potential way to improve the energy efficiency of computers beyond von Neumann-Landauer limit. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this paper, a new 4*4 reversible logic gate SDNG is proposed. The SDNG gate can be used to implement all types of classical Boolean applications like XOR, XNOR, NAND, NOR, AND, OR, and NOT. It also can be used to design various adders efficiently. One of the prominent functionalities of the SDNG gate is that it can work singly as a full adder, or full subtractor, which is a versatile and widely used element in digital design. Thus, the proposed reversible full adder/subtractor contains only one gate. This paper also represents 4 bit Parallel adder circuit, 4 bit Parallel subtractor circuit, 2s Complement adder-subtractor circuit, Carry skip adder circuit , BCD adder circuit and carry skip BCD adder circuit which have been implemented by using this proposed SDNG reversible gate. Also SDNG gate and SDNG gate as a full adder and full subtractor has been simulated by XILINX and implemented in the SPARTAN -FPGA Kit.
