期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2018
卷号：7
期号：1
页码：83-85
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Carry look ahead adder is by default high speed structure but with sacrificing area and power. In this paper we proposed Carry look ahead adder with low area and low power. We have designed xor and xnor cells in which it generates two outputs. Xor outputs the xor and nor logic where as xnor outputs the xnor and nand logic.We can design adder by efficiently utilizing the hardware required for sum logic to the carry logic. But the choice of using only xor or only xnor or combination of both for designing sum logic has considerable impact on the hardware requirements of the carry logic. Total transistor count for proposed 4-bit carry look ahead adder is 164 with existing design transistor count of 236.
