期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2017
卷号：6
期号：7
页码：972-975
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The main intention of this paper is to provide new low area solution for very large scale integration (VLSI) designers. At transistor level, STATIC CMOS logic style can give better results when we design N-types of circuits and then select the best one over others. In this project the proposed Adder has been designed by using STATIC CMOS 180nm TECHNOLOGY. Layout for Adder has been implemented by using tanner tool.
