期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2018
卷号：7
期号：4
页码：3410
DOI：10.15680/IJIRSET.2018.0704029
出版社：S&S Publications
摘要：In this paper, a new method to reduce the common mode voltage (CMV) at output terminal of the three level neutralpoint clamped (NPC) inverter is proposed. Space vector pulse width modulation (SVPWM) technique is used to generate gate pulsesfor the three level NPC inverter. In conventional SVPWM for three level NPC inverter, 27 voltage vectors are used. But in theproposed method only 19 voltage vectors are used in order to reduce the CMV. By using the modified method, the CMV can bereduced to about one-sixth of the DC input voltage. This technique is mainly suitable for high power, medium voltage applications.The effectiveness of the proposed method is verified using matlab simulation results.
关键词：Multilevel inverters; Space vector pulse width modulation; Neutral point clamped inverter; Common;mode voltage .
