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  • 标题:Design of Modified Carry Select Adder with Low Power and Efficient Area Using D-Latch
  • 本地全文:下载
  • 作者:B. Vijaya Lakshmi ; B. Praveen Kumar
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2018
  • 卷号:7
  • 期号:2
  • 页码:1130
  • DOI:10.15680/IJIRSET.2018.0702007
  • 出版社:S&S Publications
  • 摘要:Carry select adder (CSLA) is a one of the high speed adders used in many computational systems toperform fast arithmetic operations. Due to the rapidly growing mobile industry not only the faster arithmetic unit butalso less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binaryto Excess-1 converter (BEC).This paper proposes an efficient method which replaces the BEC using Dlatch .Experimental analysis shows that the proposed architecture achieves the three folded advantages in termsof area, delay and power.
  • 关键词:Carry select adder (CSLA) is a one of the high speed adders used in many computational systems to;perform fast arithmetic operations. Due to the rapidly growing mobile industry not only the faster arithmetic unit but;also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary;to Excess-1 converter (BEC).This paper proposes an efficient method which replaces the BEC using D;latch .Experimental analysis shows that the proposed architecture achieves the three folded advantages in terms;of area; delay and power.
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