期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2018
卷号：6
期号：3
页码：2361
DOI：10.15680/IJIRCCE.2017.0603109
出版社：S&S Publications
摘要：With the advent of new technology in the fields of VLSI and communication, there is also an evergrowing demand for high speed processing and low area design. It is also a well-known fact that the multiplier unitforms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need ofthe day. In this paper, we have developed three designs for Urdhwa Multiplier. In first design we have developed 4:2compressors based on full adder and utilization in term of 42 delays and 21 areas. In second design we have developed4:2 compressors based on XOR gate and utilization in term of 36 delays and 24 areas. In third design we havedeveloped 4:2 compressors based on full adder and utilization in term of 28 delays and 18 areas.
关键词：4:2 Compressor based on Full Adder; 4:2 Compressor based on XOR Gate; 4:2 Compressor based on;XOR-XNOR Gate
