期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2018
卷号：6
期号：3
页码：2374
DOI：10.15680/IJIRCCE.2017.0603111
出版社：S&S Publications
摘要：This paper presents efficient modified distributed arithmetic (MDA)-based approaches for low delayreconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime.Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to beimplemented in ROM; and the ROM-based LUT is found to be costly for application specific integrated circuit (ASIC)implementation. Therefore, a shared-LUT design is proposed to realize the MDA computation. Instead of usingseparate registers to store the possible results of partial inner products for DA processing of different bit positions,registers are shared by the DA units for bit slices of different weightage.
